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Data Sheet No. PD60213 revC
IR2114SS/ IR21141SS IR2214SS/IR22141SS
HALF-BRIDGE GATE DRIVER IC
Features
* * * * * * * * Floating channel up to +600 or +1200V Soft over-current shutdown Synchronization signal to synchronize shut down with the other phases Integrated desaturation detection circuit Two stage turn on output for di/dt control Separate pull-up/pull-down output drive pins Matched delay outputs Under voltage lockout with hysteresis band
Product Summary
VOFFSET IO+/- (typ) VOUT Deadtime matching (max) Deadtime (typ) Desat blanking time (typ) DSH, DSL input voltage threshold (typ) Soft shutdown time (typ) 600V or 1200V max. 2.0 A / 3.0A 10.4V - 20V 75 nsec 330 nsec 3 sec 8.0 V 9.25 sec
Description
The IR2114/21141/2214/IR22141 gate driver family is suited to drive a single half bridge in power switching applications. The high gate driving capability (2A source, 3A sink) and the low quiescent current enable bootstrap supply techniques in medium power systems. These drivers feature full short circuit protection by means of the power transistor desaturation detection and manages all the half-bridge faults by turning off smoothly the desaturated transistor through the dedicated soft shut down pin, therefore preventing over-voltages and reducing EM emissions. In multi-phase system IR2114/21141/2214/IR22141 drivers communicate using a dedicated local network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase short circuits. The system controller may force shutdown or read device fault state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the control and power ground use dedicated pins enabling low-side emitter current sensing as well. Undervoltage conditions in floating and low voltage circuits are managed independently.
Package
24-Lead SSOP
Typical connection
DC+
15 V
VCC
VB HOP HON SSDH
LIN
DC BUS (1200V)
IR2214
HIN uP, Control FAULT/SD FLT_CLR SY_FLT
DSH VS
Motor
LOP LON SSDL DSL VSS COM
DC-
1
IR2114/IR21141/IR2214/IR22141
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VS VB VHO VCC COM VLO VIN VFLT VDSH VDSL dVs/dt PD RthJA TJ TS TL Definition High side offset voltage High side floating supply voltage
(IR2114 or IR21141)
Min.
Max. VB + 0.3 625 1225 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VB + 0.3 VCC + 0.3 50 1.5 65 125 150 300
Units
VB - 25 -0.3 -0.3 (IR2214 or IR22141) High side floating output voltage (HOP, HON and SSDH) VS - 0.3 Low side and logic fixed supply voltage -0.3 Power ground VCC - 25 Low side output voltage (LOP, LON and SSDL) VCOM -0.3 Logic input voltage (HIN, LIN and FLT_CLR) VSS -0.3 FAULT input/output voltage (FAULT/SD and SY_FLT) VSS -0.3 High side DS input voltage VS -3 Low side DS input voltage VCOM -3 Allowable offset voltage slew rate -- Package power dissipation @ TA +25C -- Thermal resistance, junction to ambient -- Junction temperature -- Storage temperature -55 Lead temperature (soldering, 10 seconds) --
V
V/ns W C/W C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential. Symbol VB VS Definition High side floating supply voltage (Note 1) High side floating supply offset (IR2114 or IR21141) voltage (IR2214 or IR22141) Min. Max. Units
VS + 11.5 VS + 20 Note 2 600 Note 2 1200 VHO High side output voltage (HOP, HON and SSDH) VS VS + 20 VLO Low side output voltage (LOP, LON and SSDL) VCOM VCC V VCC Low side and logic fixed supply voltage (Note 1) 11.5 20 COM Power ground -5 5 VIN Logic input voltage (HIN, LIN and FLT_CLR) VSS VCC VFLT Fault input/output voltage (FAULT/SD and SY_FLT) VSS VCC VDSH High side DS pin input voltage VS - 2.0 VB VDSL Low side DS pin input voltage VCOM - 2.0 VCC TA Ambient temperature -40 125 C Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached. Note 2: Logic operational for VS from VSS-5V to VSS+600V or 1200V. Logic state held for VS from VSS-5V to VSS-VBS. (Please refer to the Design Tip DT97-3 for more details).
2
IR2114/IR21141/IR2214/IR22141
Static Electrical Characteristics
VCC = 15 V, VSS = COM = 0 V, VS = 0 / 600V or 1200 V and TA = 25 C unless otherwise specified. Pin: VCC, VSS, VB, VS
Symbol VCCUV+ VCCUVVCCUVH VBSUV+ VBSUVVBSUVH ILK IQBS IQCC Definition Vcc supply undervoltage positive going threshold Vcc supply undervoltage negative going threshold Vcc supply undervoltage lockout hysteresis (VB-VS) supply undervoltage positive going threshold (VB-VS) supply undervoltage negative going threshold (VB-VS) supply undervoltage lockout hysteresis Offset supply leakage current Quiescent VBS supply current Quiescent Vcc supply current
comparator VCC/VB UV internal signal
Min Typ Max Units Test Conditions 9.3 10.2 11.4 8.7 9.3 10.3 0.9 9.3 10.2 11.4 V VS=0V, VS=600V or 1200V 8.7 9.3 10.3 VS=0V, VS=600V or 1200V 0.9 50 VB = VS = 600V or 1200V A 400 800 VIN = 0V or 3.3V 0.7 2.5 mA (No load)
VCCUV/VBSUV VSS/VS
Figure 1: Undervoltage diagram
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol VIH VIL Definition Logic "1" input voltage Logic "0" input voltage Logic input hysteresis Logic "1" input bias current Logic "0" input bias current FAULT/SD open drain resistance SY_FLT open drain resistance
schmitt trigger HIN/LIN/ FLTCLR 10k internal signal
VIHSS
IIN+ IINRON,FLT RON,SY
Min 2.0 0.2 -1 -
Typ 0.4 370 60 60
Max Units Test Conditions VCC = VCCUV- to V 0.8 20V 0 A VIN = 3.3V VIN = 0V PW 7 s
VSS
Figure 2: HIN, LIN and FLTCLR diagram
3
IR2114/IR21141/IR2214/IR22141
FAULT/SD SY_FLT
fault/hold internal signal
schmitt trigger RON
hard/soft shutdown internal signal
VSS
Figure 3: FAULT/SD and SY_FLT diagram
Pin: DSL, DSH
The active bias is present only in IR21141 and IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS respectively for DSL and DSH. Symbol Definition Min Typ Max Units Test Conditions VDESAT+ VDESATVDSTH IDS+ IDSIDSB High desat input threshold voltage Low desat input threshold voltage Desat input voltage hysteresis High DSH or DSL input bias current Low DSH or DSL input bias current DSH or DSL input bias current (IR21141 and IR22141 only)
VCC/VBS
7.2 8.0 8.8 6.3 7.0 7.7 1.0 21 - -160 -20 -
V A mA
See Fig. 16, 4 VDESAT = VCC or VBS VDESAT = 0V VDESAT = (VCC or VBS) - 2V
100k
active bias comparator
DSL/DSH VDESAT
SSD 700k
internal signal
COM/VS
Figure 4: DSH and DSL diagram.
4
IR2114/IR21141/IR2214/IR22141
Pin: HOP, LOP
Symbol VOH IO1+ Definition High level output voltage, VB - VHOP or Vcc -VLOP Output high first stage short circuit pulsed current Min Typ Max Units Test Conditions IO = 20mA 40 300 mV 2 VHOP/LOP=0V, HIN or LIN= 1, PW200ns, resistive load, see Fig. 8 A 1 VHOP/LOP=0V, HIN or LIN = 1, 400nsPW10s, resistive load, see Fig. 8
IO2+
Output high second stage short circuit pulsed current
200ns oneshot
VCC/VB
VOH
on/off internal signal
LOP/HOP
Figure 5: HOP and LOP diagram
Pin: HON, LON, SSDH, SSDL
Symbol VOL RON,SSD IODefinition Low level output voltage, VHON or VLON Soft Shutdown on resistance (Note 1) Output low short circuit pulsed current Min Typ Max Units Test Conditions IO = 20mA 45 300 mV 90 PW 7 s 3 A VHOP/LOP=15V, HIN or LIN = 0, PW10s
Note 1: SSD operation only.
LON/HON
on/off internal signal desat internal signal
SSDL/SSDH VOL RON,SSD
COM/VS
Figure 6: HON, LON, SSDH and SSDL diagram
5
IR2114/IR21141/IR2214/IR22141
AC Electrical Characteristics
VCC = VBS = 15V, VS = VSS and TA = 25C unless otherwise specified. Symbol ton toff tr tf ton1 tDESAT1 tDESAT2 tDESAT3 tDESAT4 tDS tSS tSY_FLT,
DESAT1
Definition Turn on propagation delay Turn off propagation delay Turn on rise time (CLOAD=1nF) Turn off fall time (CLOAD=1nF) Turn on first stage duration time DSH to HO soft shutdown propagation delay at HO turn on DSH to HO soft shutdown propagation delay after Blanking DSL to LO soft shutdown propagation delay at LO turn on DSL to LO soft shutdown propagation delay after Blanking Soft shutdown minimum pulse width of desat Soft shutdown duration period DSH to SY_FLT propagation delay at HO turn on DSH to SY_FLT propagation delay after blanking DSL to SY_FLT propagation delay at LO turn on DSL to SY_FLT propagation delay after blanking DS blanking time at turn on
Min. Typ. Max. Units 220 440 220 440 -- 24 660 660 --
Test Conditions VIN = 0 & 1 VS = 0 to 600V or 1200V HOP shorted to HON, LOP shorted to LON, Figure 7 Figure 8 VHIN= 1 VDESAT = 15V,Fig.10
-- 7 -- 120 200 280 2000 3300 4600 1050 -- --
2000 3300 4600 1050 -- 1000 -- -- -- ns VLIN = 1 VDESAT = 15V,Fig.10 Figure 9 VDS=15V,Fig. 9 VHIN = 1 VDS = 15V, Fig. 10
5000 9250 13500 -- 3600 1300 -- -- 3050 1050 -- -- 3000 -- -- -- -- --
tSY_FLT,
DESAT2
tSY_FLT,
DESAT3
tSY_FLT,
DESAT4
VLIN = 1 VDESAT=15V,Fig.10 VHIN = VLIN = 1 VDESAT=15V,Fig.10 Figure 11 External DT=0nsec Figure 11 External DT> 500nsec, Fig.7
tBL
Dead-time/Delay Matching Characteristics DT MDT PDM Dead-time Dead-time matching, MDT=DTH-DTL Propagation delay matching, Max(ton, toff) - Min(ton, toff) -- -- -- 330 -- -- -- 75 75
6
IR2114/IR21141/IR2214/IR22141
3.3V HIN LIN t on 50% tr PW out HO (HOP=HON) LO (LOP=LON) 90% 10%
Figure 7: Switching Time Waveforms
PW in
50% t off
tf
90% 10%
Ton1 Io1+ Io2+
Figure 8: Output Source Current
3.3V HIN/LIN
t DS
DSH/DSL 8V 8V
SSD Driver Enable
t DESAT
t SS
HO/LO
Figure 9: Soft Shutdown Timing Waveform
7
IR2114/IR21141/IR2214/IR22141
HIN
50%
50%
LIN
50%
DSH
8V
8V
DSL
8V
8V
SY_FLT
tSY_FLT,
50%
DESAT1
50%
tSY_FLT,
50%
DESAT3
50%
tSY_FLT,DESAT2
tSY_FLT,DESAT4
FAULT/SD
FLTCLR
tDESAT1
10%
tDESAT2
90% SoftShutdown
Turn_Off propagation Delay
50%
50%
90% SoftShutdown
90%
HON
tBL
Turn-On Propagation Delay
tBL
10%
tDESAT3
50%
90% SoftShutdown
tDESAT4
50%
90% SoftShutdown 90%
LON
tBL
Turn-On Propagation Delay
tBL
Figure 10: Desat Timing
LIN HIN
50%
50%
HO (HOP=HON) LO (LOP=LON)
50%
DTH
50%
DTL
50%
MDT=DTH-DTL
Figure 11: Internal Dead-Time Timing
50%
8
IR2114/IR21141/IR2214/IR22141
Lead Assignments
HIN LIN FLT_CLR SY_FLT FAULT/SD
1
24
DSH VB N.C. HOP HON
24-Lead SSOP
VSS SSDL COM LON LOP VCC DSL 12
SSOP24
VS SSDH N.C. N.C. N.C. N.C. 13 N.C.
Lead Definitions
Symbol VCC VSS HIN LIN Description Low side gate driver supply Logic Ground Logic input for high side gate driver outputs (HOP/HON) Logic input for low side gate driver outputs (LOP/LON) Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault FAULT/SD condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status. Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD SY_FLT sequence is occurring. As an input, an active low signal freezes both output status. FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17) LOP Low side driver sourcing output LON Low side driver sinking output DSL Low side IGBT desaturation protection input SSDL Low side soft shutdown COM Low side driver return VB High side gate driver floating supply HOP High side driver sourcing output HON High side driver sinking output DSH High side IGBT desaturation protection input SSDH High side soft shutdown VS High side floating supply return
9
IR2114/IR21141/IR2214/IR22141
Functional Block Diagram
VCC
SCHMITT TRIGGER INPUT SHOOT THROUGH PREVENTION (DT) Deadtime INPUT HOLD LOGIC OUTPUT SHUTDOWN LOGIC
VB
on/off on/off (HS)
LEVEL SHIFTERS
HIN LIN
on/off
LATCH LOCAL DESAT PROTECTION
soft shutdown
di/dt control Driver
HOP HON SSDH DSH
on/off (LS)
desat
SOFT SHUTDOWN UV_VBS DETECT
Hard ShutDown
internal Hold
VS
UV_VCC DETECT
UV_VCC DesatHS
on/off
SY_FLT FAULT/SD FLT_CLR
SSD FAULT
HOLD SD
FAULT LOGIC managemend (See figure 14)
DesatLS
LOCAL DESAT PROTECTION SOFTSHUTDOWN
soft shutdown
di/dt control Driver
LOP LON SSDL DSL
VSS
COM
State Diagram
Start-Up Sequence
SY _F
LT
FAULT
/SD
HO=LO=0
IN
FA U LT/S D
ShutDown
FL T_ CL R
HI N/ L
VCC UV_
FA
D /S LT U
VB V_ U S
FAULT DESAT EVENT
/LIN HIN
UnderVoltage VCC HO=LO=0
UnderVoltage VBS HO=0, LO=LIN UV_VCC
L _F SY
HO/LO=1 Soft ShutDown
L H/ DS
C _ VC UV
T
FAU
Freeze
DS H/ L
Stable State
- FAULT - SOFT SHUTDOWN - FLT_CLR - HO=LO=0 (Normal operation) - START UP SEQUENCE - HIN/LIN - HO/LO=1 (Normal operation) - UV_VCC - UNDERVOLTAGE VCC - UV_VBS - SHUTDOWN (SD) - DSH/L - UNDERVOLTAGE VBS - SY_FLT - FREEZE - FAULT/SD NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event happens in HIN.
Temporary State
FA
LT/S D
UL T/ SD
UV_VBS
FLT SY_
System Variable
10
IR2114/IR21141/IR2214/IR22141
Logic Table
Output drivers status description HO/LO HOP/LOP HON/LON status
0 1 SSD LO/HO
LOn-1/HOn-1
SSDH/SSDL
HiZ HiZ 0
HiZ 1 HiZ
0 HiZ HiZ
Output follows inputs (in=1->out=1, in=0->out=0)
Output keeps previous status
Under Voltage
INPUTS
SY_FLT Hin Lin
INPUT/OUTPUT
FAULT/SD
SD: shutdown (in) FAULT: diagnostic (out) SSD: desat (out) HOLD: freezing (in)
Yes: V< UV threshold No : V> UV threshold X : don't care
OUTPUTS
HO LO
VCC
VBS
Operation
Shut Down Fault Clear
FLT_CLR
X HIN 1 0 0 1 1 0 X X X X
X LIN 0 1 0 1 0 1 X X X LIN
X 0 0 0 0 0 0 0 0 X X
X
NOTE1
0 (SD)
(FAULT)
X No No No No No No No No No No No
X No No No No No No No No No No Yes
0 HO 1 0 0 0 SSD 0 0 0 HOn-1 0
0 LO 0 1 0 0 0 SSD 0 0 LOn-1 LO
1 1 1 1
(SSD) (SSD) (SSD) (SSD)
1 1 1 1 1 1
(FAULT) (FAULT)
Normal Operation Anti Shoot Through Soft Shut Down (entering) Soft Shut Down (finishing) Freeze Under Voltage
0 (HOLD) 1
1 1
X X X 1 0 (FAULT) Yes X 0 0 NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required. In order to avoid FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active.
11
IR2114/IR21141/IR2214/IR22141
FEATURES DESCRIPTION
1 Start-up sequence
At power supply start-up it is recommended to keep FLT_CLR pin active until supply voltages are properly established. This prevents spurious diagnostic signals being generated. All protection functions are operating independently from FLT_CLR status and output driver status reflects the input commands. When bootstrap supply topology is used for supplying the floating high side stage, the following start-up sequence is recommended (see also figure 12): 1. Set Vcc 2. Set FLT_CLR pin to HIGH level 3. Set LIN pin to HIGH level and let the bootstrap capacitor be charged 4. Release LIN pin to LOW level 5. Release FLT_CLR pin to LOW level
VCC FLT_CLR LIN
both low and high side circuits) desaturation of both power transistors.
and
the
4.1 Undervoltage (UV)
The Undervoltage protection function disables the driver's output stage preventing the power device being driven with too low voltages. Both the low side (VCC supplied) and the floating side (VBS supplied) are controlled by a dedicate undervoltage function. Undervoltage event on the VCC (when VCC < UVVCC-) generates a diagnostic signal by forcing FAULT/SD pin low (see FAULT/SD section and figure 14). This event disables both low side and floating drivers and the diagnostic signal holds until the under voltage condition is over. Fault condition is not latched and the FAULT/SD pin is released once VCC becomes higher than UVVCC+. The undervoltage on the VBS works disabling only the floating driver. Undervoltage on VBS does not prevent the low side driver to activate its output nor generate diagnostic signals. VBS undervoltage condition (VBS < UVVBS-) latches the high side output stage in the low state. VBS must be reestablished higher than UVVBS+ to return in normal operating mode. To turn on the floating driver HIN must be re-asserted high (rising edge event on HIN is required).
LO
4.2 Power devices desaturation
Different causes can generate a power inverter failure: phase and/or rail supply short-circuit, overload conditions induced by the load, etc... In all these fault conditions a large current increase is produced in the IGBT. The IR2114/21141/2214/22141 fault detection circuit monitors the IGBT emitter to collector voltage (VCE) by means of an external high voltage diode. High current in the IGBT may cause the transistor to desaturate, i.e. VCE to increase. Once in desaturation, the current in power transistor can be as high as 10 times the nominal current. Whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltages). The gate driver accomplishes the transients control by smoothly turning off the desaturated transistor by means of the SSD pin activating a so called Soft ShutDown sequence (SSD). 4.2.1 Desaturation detection: DSH/L function Figure 13 shows the structure of the desaturation sensing and soft shutdown block. This configuration is the same for both high and low side output stages.
Figure 12 Start-up sequence A minimum 15 us LIN and FLT-CLR pulse is required.
2 Normal operation mode
After start-up sequence has been terminated, the device becomes fully operative (see grey blocks in the State Diagram). HIN and LIN produce driver outputs to switch accordingly, while the input logic checks the input signals preventing shoot-through events and including DeadTime (DT).
3 Shut down
The system controller can asynchronously command the Hard ShutDown (HSD) through the 3.3 V compatible CMOS I/O FAULT/SD pin. This event is not latched. In a multi-phase system, FAULT/SD signals are orwired so the controller or one of the gate drivers can force simultaneous shutdown to the other gate drivers through the same pin.
4 Fault management
IR2114/21141/2214/22141 is able to manage the both the supply failure (undervoltage lock out on
12
IR2114/IR21141/IR2214/IR22141
VB/Vcc
PreDriver
on/off
sensing diode
HOPH/L
ONE SHOT (ton1)
HONH/L
tBL Blanking
DesatHS/LS
RDSH/L
tss One Shot
Ron,ss
SSDH/L
tDS filter
desat comparator
DSH/L
VDESAT
VS/COM
Figure 13: high and low side output stage
internal HOLD internal FAULT (hard shutdown)
SY_FLT (external hold)
FAULT/SD (external hard shutdown)
Q Q
SET
S R
DesatHS DesatLS UVCC
CLR
FLTCLR
Figure 14: fault management diagram The external sensing diode should have BV>600V or 1200V and low stray capacitance (in order to minimize noise coupling and switching delays). The diode is biased by an internal pull-up resistor RDSH/L (equal to VCC/IDS- or VBS/IDS- for IR2114 or IR2214) or by a dedicated circuit (see the activebias section for IR21141 and IR22141). When VCE increases, the voltage at DSH/L pin increases too. Being internally biased to the local supply, DSH/L voltage is automatically clamped. When DSH/L exceeds the VDESAT+ threshold the comparator triggers (see figure 13). Comparator output is filtered in order to avoid false desaturation detection by externally induced noise; pulses shorter than tDS are filtered out. To avoid detecting a false desaturation during IGBT turn on, the desaturation circuit is disabled by a Blanking signal (TBL, see Blanking block in figure 13). This time is the estimated maximum IGBT turn on time and must be not exceeded by proper gate resistance sizing. When the IGBT is not completely saturated after TBL, desaturation is detected and the driver will turn off. Eligible desaturation signals initiate the Soft Shutdown sequence (SSD). While in SSD, the output driver goes in high impedance and the SSD pull-down is activated to turn off the IGBT through SSDH/L pin. The SY_FLT output pin (active low, see figure 14) reports the gate driver status all the way long SSD sequence lasts (tSS). Once finished SSD, SYS_FLT releases, and the gate driver generates a FAULT signal (see the FAULT/SD section) by activating FAULT/SD pin. This generates a hard shut down for both high and low output stages (HO=LO=low). Each driver is latched low until the fault is cleared (see FLT_CLR). Figure 14 shows the fault management circuit. In this diagram DesatHS and DesatLS are two internal signals that come from the output stages (see figure 13). It must be noted that while in Soft Shut Down, both Under Voltage fault and external Shut Down (SD)
13
IR2114/IR21141/IR2214/IR22141
are masked until the end of SSD. Desaturation protection is working independently by the other entire control pin and it is disabled only when the output status is off. 3. FAULT/SD is externally driven low either from the controller or from another IR2x14x device. This event is not latched; therefore the FLT_CLR cannot disable it. Only when FAULT/SD becomes high the device returns in normal operating mode.
FAULT
5 Active bias
VCC LIN HIN FLT_CLR VB HOP HON SSH VCC LIN HIN FLT_CLR VB HOP HON SSH VCC LIN HIN FLT_CLR SY_FLT VB HOP HON SSH
IR2214
IR2214
SY_FLT
SY_FLT
VS
VS
IR2214
DSH
DSH
DSH VS
FAULT/SD
LOP LON SSL DSL
FAULT/SD
LOP LON SSL DSL
FAULT/SD
LOP LON SSL DSL
VSS
COM
VSS
COM
VSS
COM
phase U
phase V
phase W
Figure 15: IR2x14x application in 3ph system. 4.2.2 Fault management in multi-phase systems In a system with two or more gate drivers the devices must be connected as in figure 15. SY_FLT. The bi-directional SY_FLT pins communicate each other in the local network. The logic signal is active low. The device that detects the IGBT desaturation activates the SY_FLT, which is then read by the other gate drivers. When SYS_FLT is active all the drivers hold their output state regardless the input signals (HIN, LIN) they receive from the controller (freeze state). This feature is particularly important in phase-tophase short circuit where two IGBTs are involved; in fact, while one is softly shutting-down, the other must be prevented from hard shutdown to avoid vanishing SSD. In the Freeze state the frozen drivers are not completely inactive because desaturation detection still takes the highest priority. SY_FLT communication has been designed for creating a local network between the drivers. There is no need to wire SY_FLT to the controller. FAULT/SD The bi-directional FAULT/SD pins communicates each other and with the system controller. The logic signal is active low. When low, the FAULT/SD signal commands the outputs to go off by hard shutdown. There are three events that can force FAULT/SD low: 1. Desaturation detection event: the FAULT\SD pin is latched low when SSD is over, and only a FLT_CLR signal can reset it. 2. Undervoltage on VCC: the FAULT\SD pin is forced low and held until the undervoltage is active (not latched).
For the purpose of sensing the power transistor desaturation the collector voltage is read by an external HV diode. The diode is normally biased by an internal pull up resistor connected to the local supply line (VB or VCC). When the transistor is "on" the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. In the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see figure 19). In fact, too low pull up resistor value may result in high current discharging significantly the bootstrap capacitor. For that reason typical pull up resistor are in the range of 100 k. This is the value of the internal pull up. While the impedance of DSH/DSL pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. In that case relevant dV/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (DSH/L). This coupled noise may be easily reduced using an active bias for the sensing diode. An Active Bias structure is available only for IR21141 or IR22141 version for DSH/L pin. The DSH/L pins present an active pull-up respectively to VB/VCC, and a pull-down respectively to VS/COM. The dedicated biasing circuit reduces the impedance on the DSH/L pin when the voltage exceeds the VDESAT threshold (see figure 16). This low impedance helps in rejecting the noise providing the current inject by the parasitic capacitance. When the power transistor is fully on, the sensing diode gets forward biased and the voltage at the DSH/L pin decreases. At this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in figure 16.
RDSH/L
100K ohm
100 ohm
VDSH/L
VDESAT+ VDESAT-
Figure 16: RDSH/L Active Biasing
14
IR2114/IR21141/IR2214/IR22141
6 Output stage
The structure is shown in figure 13 and consists of two turns on stages and one turn off stage. When the driver turns on the IGBT (see figure 8), a first stage is constantly activated while an additional stage is maintained active only for a limited time (ton1). This feature boost the total driving capability in order to accommodate both fast gate charge to the plateau voltage and dV/dt control in switching.
A B C
At turn off, a single n-channel sinks up to 3A (IO-) and offers a low impedance path to prevent the self-turn on due to the parasitic Miller capacitance in the power switch.
7 Timing and logic state diagrams description
The following figures show the input/output logic diagram. Figure 17 shows the SY_FLT and FAULT/SD signals as output, whereas figure 18 as input.
D E F G
HIN LIN
DSH DSL SY_FLT FAULT/SD
FLT_CLR HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output
AB C D E F
HIN LIN SY_FLT FAULT/SD FLT_CLR HO (HOP/HON) LO (LOP/LON)
Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input Referred to timing diagram of figure 17: A. When the input signals are on together the outputs go off (anti-shoot through). B. The HO signal is on and the high side IGBT desaturates, the HO turn off softly while the SY_FLT stays low. When SY_FLT goes high the FAULT/SD goes low. While in SSD, if LIN goes up, LO does not change (freeze). C. When FAULT/SD is latched low (see FAULT/SD section) FLT_CLR can disable
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IR2114/IR21141/IR2214/IR22141
it and the outputs go back to follow the inputs. The DSH goes high but this is not read because HO is off. The LO signal is on and the low side IGBT desaturates, the low side behaviour is the same as described in point B. The DSL goes high but this is not read because LO is off. As point A (anti-shoot through). This method has the advantage of being simple and low cost but may force some limitations on duty-cycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations.
D. E. F. G.
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to establish the minimum voltage drop (VBS) that we have to guarantee when the high side IGBT is on. If VGEmin is the minimum gate emitter voltage we want to maintain, the voltage drop must be:
Referred to timing diagram figure 18: A. The device is in hold state, regardless of input variations. Hold state is forced by SY_FLT forced low externally B. The device outputs goes off by hard shutdown, externally commanded. A through B is the same sequence adopted by another IR2x14x device in SSD procedure. C. Externally driven low FAULT/SD (shutdown state) cannot be disabled by forcing FLT_CLR (see FAULT/SD section). D. The FAULT/SD is released and the outputs go back to follow the inputs. E. Externally driven low FAULT/SD: outputs go off by hard shutdown (like point B). F. As point A and B but for the low side output.
VBS VCC - VF - VGE min - VCEon
under the condition:
VGE min > VBSUV -
where VCC is the IC voltage supply, VF is bootstrap diode forward voltage, VCEon is emitter-collector voltage of low side IGBT and VBSUV- is the highside supply undervoltage negative going threshold. Now we must consider the influencing factors contributing VBS to decrease: - - - - - - - IGBT turn on required Gate charge (QG); IGBT gate-source leakage current (ILK_GE); Floating section quiescent current (IQBS); Floating section leakage current (ILK) Bootstrap diode leakage current (ILK_DIODE); Desat diode bias when on (IDS- ) Charge required by the internal level shifters (QLS); typical 20nC - Bootstrap capacitor leakage current (ILK_CAP); - High side on time (THON).
Sizing tips
Bootstrap supply
The VBS voltage provides the supply to the high side driver circuitry of the gate driver. This supply sits on top of the VS voltage and so it must be floating. The bootstrap method to generate VBS supply can be used with any of the IR2114, IR21141, IR2214, IR22141. The bootstrap supply is formed by a diode and a capacitor connected as in figure 19.
bootstrap resistor Rboot bootstrap diode DC+
VF
VCC VCC
VB
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution). Then we have:
HOP VBS HON VS SSDH VCEon VFP bootstrap capacitor VGE ILOAD motor
IR2214
QTOT = QG + Q LS + ( I LK _ GE + I QBS +
+ I LK + I LK _ DIODE + I LK _ CAP + I DS - ) THON
The minimum size of bootstrap capacitor is:
COM
Figure 19: bootstrap supply schematic
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IR2114/IR21141/IR2214/IR22141
C BOOT min = QTOT V BS
the Vs node is pushed up by the load current until the high side freewheeling diode get forwarded biased ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
An example follows using IR2214SS or IR22141SS: a) using a 25A @ 125C 1200V IGBT (IRGP30B120KD): * * * * * * IQBS = 800 A (This Datasheet); (See Static Electrical Charact.); ILK = 50 A QLS = 20 nC; (Datasheet IRGP30B120KD); QG = 160 nC ILK_GE = 100 nA (Datasheet IRGP30B120KD); ILK_DIODE = 100 A (with reverse recovery time <100 ns); * ILK_CAP = 0 (neglected for ceramic capacitor); * IDS- = 150 A (see Static Electrical Charact.); * THON = 100 s.
VBS = VCC - V F
ILOAD > 0; the load current flows through the freewheeling diode
VBS = VCC - V F + VFP
In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. To minimize the risk of undervoltage, bootstrap capacitor should be sized according to the ILOAD<0 case. b. Bootstrap Resistor A resistor (Rboot) is placed in series with bootstrap diode (see figure 19) so to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding some Ohms (typically 5, maximum 10 Ohm) to avoid increasing the VBS time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. c. Bootstrap Capacitor For high THON designs where is used an electrolytic tank capacitor, its ESR must be considered. This parasitic resistance forms a voltage divider with Rboot generating a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint:
And: * * * * VCC = 15 V VF = 1 V VCEonmax = 3.1 V VGEmin = 10.5 V
the maximum voltage drop VBS becomes
VBS VCC - VF - VGEmin - VCEon = = 15V - 1V - 10.5V - 3.1V = 0.4V
And the bootstrap capacitor is:
CBOOT
290 nC = 725 nF 0.4 V
NOTICE: Here above VCC has been chosen
to be 15V. Some IGBTs may require higher supply to work correctly with the bootstrap technique. Also Vcc variations must be accounted in the above formulas.
ESR VCC 3V ESR + RBOOT
Parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge thank for the gate charge only and limiting the dVBS/dt by reducing the equivalent resistance while the second keeps the VBS voltage drop inside the desired VBS. d. Bootstrap Diode The diode must have a BV> 600V or 1200V and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to VCC supply.
Some important considerations
a. Voltage ripple There are three different cases making the bootstrap circuit gets conductive (see figure 19) ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon
VBS = VCC - VF - VCEon
In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off
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IR2114/IR21141/IR2214/IR22141
Gate resistances
The switching speed of the output transistor can be controlled by properly size the resistors controlling the turn-on and turn-off gate current. The following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver (RDRp and RDRn). The examples always use IGBT power transistor. Figure 20 shows the nomenclature used in the following paragraphs. In addition, Vge* indicates the plateau voltage, Qgc and Qge indicate the gate to collector and gate to emitter charge respectively.
CRES IC
Vcc/Vb RDRp RGon COM/Vs
Iavg CRES
Figure 21: RGon sizing where RTOT = RDRp + RGon RGon = gate on-resistor RDRp = driver equivalent on-resistance When RGon > 7 Ohm, RDRp is defined by
VGE
t1,QGE VCE
t2,QGC dV/dt IC
RDRp
Vcc Vcc t SW + t - 1 when t SW > t on1 I I o 2+ on1 = o1+ Vcc when t SW t on1 I o1+
ton1 from "static Electrical
90%
CRES VGE
CRESon
Vge*
(IO1+ ,IO2+ and Characteristics").
CRESoff
10% 10%
t,Q tSW tDon tR
Table 1 reports the gate resistance size for two commonly used IGBTs (calculation made using typical datasheet values and assuming Vcc=15V).
- Output voltage slope
Turn-on gate resistor RGon can be sized to control output slope (dVOUT/dt). While the output voltage has a non-linear behaviour, the maximum output slope can be approximated by:
Figure 20: Nomenclature
Sizing the turn-on gate resistor - Switching-time
For the matters of the calculation included hereafter, the switching time tsw is defined as the time spent to reach the end of the plateau voltage (a total Qgc+Qge has been provided to the IGBT gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and Qgc, Vcc, Vge* (see figure 21):
I avg dVout = dt C RESoff
inserting the rearranging: expression
*
yielding
Iavg
and
I avg =
and
Qgc + Qge t sw
RTOT
Vcc - Vge = dV C RESoff out dt
RTOT =
* Vcc - V ge
As an example, table 2 shows the sizing of gate resistance to get dVout/dt=5V/ns when using two popular IGBTs, typical datasheet values and assuming Vcc=15V.
I avg
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IR2114/IR21141/IR2214/IR22141
NOTICE: Turn on time must be lower than TBL to avoid improper desaturation detection and SSD triggering. As a result, when is faster than the collector rise time (to be verified after calculation) the transfer function can be approximated by:
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor RGoff is when the collector of the IGBT in off state is forced to commutate by external events (i.e. the turn-on of the companion IGBT). In this case the dV/dt of the output node induces a parasitic current through CRESoff flowing in RGoff and RDRn (see figure 22). If the voltage drop at the gate exceeds the threshold voltage of the IGBT, the device may self turn on causing large oscillation and relevant cross conduction.
Vge Vde
= s ( RGoff + RDRn ) CRESoff
dVde in the dt
So that Vge = ( RGoff + RDRn ) CRESoff time domain. Then the condition:
Vth > Vge = (RGoff + RDRn ) CRESoff
dVout dt
must be verified to avoid spurious turn on. Rearranging the equation yields:
HS Turning ON
dV/dt
CRESoff RGoff OFF ON RDRn C IES
RGoff <
Vth CRESoff
dV dt
- RDRn
In any case, the worst condition for unwanted turn on is with very fast steps on IGBT collector. In that case collector to gate transfer function can be approximated with the capacitor divider:
Figure 22: RGoff sizing: current path when Low Side is off and High Side turns on The transfer function between IGBT collector and IGBT gate then becomes:
Vge = Vde
CRESoff (CRESoff + CIES )
which is driven only by IGBT characteristics. As an example, table 3 reports RGoff (calculated with the above mentioned disequation) for two popular IGBTs to withstand dVout/dt = 5V/ns. NOTICE: the above-described equations are intended being an approximated way for the gate resistances sizing. More accurate sizing may account more precise device modelling and parasitic component dependent on the PCB and power section layout and related connections.
Vge Vde
=
s ( RGoff + RDRn ) CRESoff 1 + s ( RGoff + RDRn ) (CRESoff + CIES )
1 + RDRn ) (CRESoff + CIES )
Which yields to a high pass filter with a pole at:
1/ =
( RGoff
Table 1: tsw driven RGon sizing
IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19nC 10nC Qgc 82nC 20nC Vge* 9V 9V tsw 400ns 200ns Iavg 0.25A 0.15A Rtot 24 40 RGon std commercial value RTOT - RDRp = 12.7 10 RTOT - RDRp = 32.5 33 Tsw
420ns 202ns
Table 2: dVOUT/dt driven RGon sizing
IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19nC 10nc Qgc 82nC 20nC Vge* 9V 9V CRESoff 85pF 14pF Rtot 14 85 RGon std commercial value RTOT - RDRp = 6.5 8.2 RTOT - RDRp = 78 82 dVout/dt
4.5V/ns 5V/ns
Table 3: RGoff sizing
IGBT IRGP30B120K(D) IRG4PH30K(D) Vth(min) 4 3 CRESoff 85pF 14pF RGoff RGoff 4 RGoff 35
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IR2114/IR21141/IR2214/IR22141
PCB LAYOUT TIPS
Distance from H to L voltage:
The IR2x14x pin out maximizes the distance between floating (from DC- to DC+) and low voltage pins. It's strongly recommended to place components tied to floating voltage in the high voltage side of device (VB, VS side) while the other components in the opposite side.
Routing and placement example:
Figure 24 shows one of the possible layout solutions using a 3 layer PCB. This example takes into account all the previous considerations. Placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize respectively supply path and gate drive loop. The bootstrap diode is placed under the device to have the cathode as close as possible to bootstrap capacitor and the anode far from high voltage and close to VCC.
Ground plane:
Ground plane must not be placed under or nearby the high voltage floating side to minimize noise coupling.
VGH
R2 R3 R4 IR2214 R5 R6 R7 C2
D2
DC+
Gate drive loops:
Current loops behave like an antenna able to receive and transmit EM noise. In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 23 shows the high and low side gate loops. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. For this reason is strongly recommended to place the three gate resistances close together and to minimize the loop area (see figure 23).
VGL
D3
Phase
a)
C1
VEH
D1
VCC VEL
R1
b)
IGC VB/ VCC H/LOP H/LON SSDH/L
Gate Drive Loop gate resistance
CGC
VGE
VS/COM
Figure 23: gate drive loop
c)
Figure 24: layout example: top (a), bottom (b) and ground plane (c) layer Referred to figure 24: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3
Supply capacitors:
IR2x14x output stages are able to quickly turn on IGBT with up to 2 A of output current. The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance.
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IR2114/IR21141/IR2214/IR22141
Case Outline
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This product has been designed and qualified for industrial market Data and specifications subject to change without notice. 3/24/2005
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